The present invention relates to a semiconductor test system, and a monitor apparatus and a filter device incorporated with the semiconductor test system for individually monitoring information on certain components used in the semiconductor test system, such as numbers of operation of relays, and for effectively maintaining such components to easily achieve high reliability of the semiconductor test system.
An example of the structure and operation of the semiconductor test system in the conventional technology will be briefly explained with reference to FIGS. 5-7.
As shown in FIG. 7, the semiconductor test system is comprised of an engineering work station (EWS) 10, a main frame 20, a test head 30, a performance board 80, and an IC socket 90.
The work station 10 is an input and output means for man/machine interfacing between the semiconductor test system and a user.
The main frame 20 includes various power sources, a tester processor, and test units for corresponding test pins (test channels) of the semiconductor test system.
The test head 30 includes a large number of printed circuit boards forming pin electronics 40 which are electronic circuits establishing a large number of test channels (test pins) noted above.
The performance board 80 is a printed circuit board designed for a specific semiconductor device to be tested (hereafter xe2x80x9cDUTxe2x80x9d). The performance board 80 is interchangeable. The IC socket 90 corresponding to the DUT is mounted on the performance board 80.
The IC socket 90 is a socket having a number of pins, size and shape corresponding to the semiconductor device to be tested.
In the semiconductor test system configured as described above, a device test proceeds as follows with reference to the block diagram of FIG. 5.
Here, in order to simplify the explanation, the diagram of FIG. 5 shows only one test channel, i.e., one pin electronics 40. However, it should be noted that a large number of such test channels are established in an actual test system. Thus, in the case where the test system has 512 test channels, 512 pin electronics 40 each being configured as shown in FIG. 5 are installed in the test system.
When conducting a DC parametric test, for example, by supplying a voltage and measuring a resultant current, a relay S12 is turned off (break) and a relay S11 is turned on (make). A direct current (DC) test unit 8 generates a test voltage which is applied to an intended pin of the DUT 91, and a current flowing through the pin is measured.
When conducting a functional test for each I/O pin of the DUT 91, the functional test is performed in the manner described in the following.
The pattern generator 5 generates a logic data, which is synchronized with the reference clock signal generated by the timing generator 4.
The wave formatter 6 generates a test pattern based on the logic data from the pattern generator 5 and the reference clock signal from the timing generator 4.
In the pin electronics 40, relays S11 and S13 are turned off and relay S12 is turned on, and the test pattern is amplified to a predetermined voltage level (VIH/VIL) by a driver D11 and is supplied to the corresponding pin of DUT 91.
The response output signal from the DUT 91 is terminated by a resistor R1 while the relay S11 is turned off and the relay S13 is turned on. Also, the relay S12 is turned on so that the output signal is converted to a logic signal by a comparator C11 and is output therefrom.
By the logic comparator 7, the resultant logic signal is compared with an expected value produced by the pattern generator 5 at the timing of a strobe signal from the timing generator 4. The logic comparator 7 determines whether the output signal of DUT 91 matches the expected value, i.e., pass or fail of the test on the DUT 91.
An example of relay control in the pin electronics 40 and the operation of functional blocks in the test system will be explained with reference to FIG. 6.
Here, it is assumed that relays S11-S1n represent relays corresponding to all of the test channels of the pin electronics in the semiconductor test system.
As shown in FIG. 6, the semiconductor test system includes the functional blocks, such as a tester processor 2 for overall control of the test system, a control unit 3, the timing generator 4, the pattern generator 5, the wave formatter 6, the logic comparator 7, and the DC test unit 8. The above noted functional blocks are connected and controlled through a tester bus 200.
The tester bus 200 is structured by lines for 8-bit address and data, for example, and control signals including clocks. The tester bus 200 serially transfers 32-bit address and 32-bit data by dividing the data into each 8-bit data.
The control unit 3 sends control signals to the test head 100. The control signals include supply voltage levels (VIH/VIL) of the drivers 11 in the pin electronics 40 and control data to a relay control circuit 31.
Although the block diagram of FIG. 6 illustrates each of the control unit 3 and other functional blocks as one unit, such unit and blocks may be combined together or a plurality of same units and blocks may be incorporated in the test system.
The relay control circuit 31 generates control signals for determining which relays of which channels should be controlled.
As an example, the relays S11-S1n are reed relays which turn on (make) or turn off (brake) by controlling the on/off of the electromagnetic coils through drivers D21-D2n. 
When three relays are used per channel for a test system of 512 test channels, then the total number of relays will be 1,536.
Since the actual number of relays used is about 3-8 per test channel depending on the type of the pin electronics, the overall number of relays becomes very large.
The relays S1-S1n will be turned on/off in a dry condition where contact points are not flowing current, or will be turned on/off in a wet condition where the contact points are flowing current.
Typically, for attaining a longer life span, the relays S11-S1n are turned on/off in the dry condition, however, they will sometimes be turned on/off in the wet condition depending on the test conditions and purposes.
The description will be made in the following regarding the maintenance of a semiconductor test system.
A semiconductor test system uses a large number of components having relatively short life spans, such as reed relays and motors, and capacitors whose performances will change with lapse of time.
Therefore, information regarding the number of operations of the relays is accumulated by a counter 1 which counts the number of ON/OFF control signals.
However, in practice, it is difficult to find an appropriate time to exchange the relays since the number of on/off operations of a relay varies depending on the test program. Further, there is a significant difference in the life span of the relays between the on/off operations in the dry condition and wet condition. Further, the total number of relays and other short-life components is large, it requires a complicated procedure to acquire sufficient information regarding the status of such components.
As described in the foregoing, in the conventional semiconductor test system, it is difficult to fully perform the maintenance work because it is not possible to obtain individual information regarding each short life component and time changing component.
Therefore, the present invention was made in view of such problems, and it is an object of the present invention to provide a semiconductor test system and an associated monitor apparatus which is capable of monitoring the test histories, for example, numbers of operations of mechanical components such as relays.
In searching the monitor information such as a test history through the tester bus, a data search and retrieve operation takes a long time if it is done by a traditional software process because it requires a time, such as 10 xcexcs, for retrieving the result data to a computer and display the result data in addition to a time for processing the measured data by the computer.
Therefore, it is not practically possible to reduce the time for retrieving the data in the conventional technology even when a high speed computer is used.
Accordingly, it is a further object of the present invention to provide a filter device for use with the semiconductor test system and monitor apparatus for improving the data search speed when retrieving the monitor information through the tester bus.
To achieve the above object, the first aspect of the present invention is a semiconductor test system which is comprised of:
a memory means for storing information concerning control signals;
an analysis means for analyzing the information on the control signals read from the memory means; and
a life-predicting means for predicting life spans of components of short life based on the analyzed information obtained by the analysis means.
To achieve the above object, the second aspect of the present invention is a semiconductor test system which is comprised of:
a memory means for storing information concerning control signals; and
an analysis means for analyzing the information on the control signals read from the memory means;
thereby monitoring a test history associated with the semiconductor test system.
To achieve the above object, the third aspect of the present invention is a semiconductor test system which is comprised of:
a memory means for storing information concerning control signals;
a filter means for retrieving information in the control signals read from the memory means based on retrieved data;
an analysis means for analyzing the information in the signal retrieved by the filter means; and
a life-predicting means for predicting life spans of components of short life based on the analyzed information obtained by the analysis means.
To achieve the above object, the fourth aspect of the present invention is a semiconductor test system for testing a semiconductor device by controlling test circuits in the test system through a tester bus and for monitoring a test history thereof, which is comprised of:
a plurality of buffer circuits for receiving signal information from the tester bus and temporarily storing the signal information therein; and
a computer for storing the signal information from the buffer circuits in a file and analyzing the signal information in the file.
To achieve the above object, the fifth aspect of the present invention is a semiconductor test system for testing a semiconductor device by controlling test circuits in the test system through a tester bus and for monitoring a test history thereof, which is comprised of:
a first buffer for receiving signal information from the tester bus and temporarily storing the signal information therein;
a second buffer for receiving signal information from the tester bus and temporarily storing the signal information therein;
a first switch means for alternately providing the signal information from the tester bus to the first buffer or the second buffer;
a second switch means for selecting the second buffer when the first switch connects to the first buffer and for selecting the first buffer when the first switch connects to the second buffer, and alternately outputting the signal information; and
a computer for storing the signal information from the second switch means in a file and analyzing the signal information in the file.
To achieve the above object, the sixth aspect of the present invention is the semiconductor test system in the third, fourth and fifth aspects of the present invention in which the monitored test history is an accumulated value of numbers of operation of relays in the semiconductor test system.
To achieve the above object, the seventh aspect of the present invention is the semiconductor test system in the sixth aspect of the present invention in which the monitored test history is an accumulated value of numbers of wet and dry operations of the relays in the semiconductor test system.
To achieve the above object, the eighth aspect of the present invention is the semiconductor test system in the sixth and seventh aspects of the present invention in which a limit number is defined for the accumulated value to display a warning signal when the accumulated value reaches the limit number.
To achieve the above object, the ninth aspect of the present invention is the semiconductor test system in the third, fourth and fifth aspects of the present invention which further comprises a filter means for allowing only predetermined signals in the signal information on the tester bus to transfer to the buffer circuit.
To achieve the above object, the tenth aspect of the present invention is a semiconductor test system for testing a semiconductor device and monitoring a test history thereof, which is comprised of:
a buffer circuit for storing control signal information regarding controls in the semiconductor test system; and
a computer for storing the signal information from the buffer circuit in a file and analyzing the signal information in the file.
To achieve the above object, the eleventh aspect of the present invention is a monitor apparatus for use with a semiconductor test system for testing a semiconductor device and monitoring a test history, which is comprised of:
a plurality of buffer circuits connected to a tester bus which controls test circuits in the semiconductor test system for alternately storing control signal information on the tester bus; and
a computer for alternately receiving the signal information from the buffer circuit and storing the signal information in a file and analyzing the signal information in the file.
To achieve the above object, the twelfth aspect of the present invention is a monitor apparatus for use with a semiconductor test system for testing a semiconductor device and monitoring a test history, which is comprised of:
a first buffer connected to a tester bus of the semiconductor test system for receiving signal information from the tester bus and temporarily storing the signal information therein;
a second buffer connected to a tester bus of the semiconductor test system for receiving signal information from the tester bus and temporarily storing the signal information therein;
a first switch means for alternately providing the signal information from the tester bus to the first buffer or the second buffer;
a second switch means for selecting the second buffer when the first switch connects to the first buffer and for selecting the first buffer when the first switch connects to the second buffer, and alternately outputting the signal information; and
a computer for storing the signal information from the second switch means in a file and analyzing the signal information in the file.
To achieve the above object, the thirteenth aspect of the present invention is the monitor apparatus for use with a semiconductor test system in the tenth, eleventh and twelfth aspects of the present invention in which the monitored test history is an accumulated value of numbers of operation of relays in the semiconductor test system.
To achieve the above object, the fourteenth aspect of the present invention is the monitor apparatus for use with a semiconductor test system in the thirteenth aspect of the present invention in which the monitored test history is an accumulated value of numbers of wet and dry operations of the relays in the semiconductor test system.
To achieve the above object, the fifteenth aspect of the present invention is the monitor apparatus for use with a semiconductor test system in the thirteenth and fourteenth aspects of the present invention in which a limit number is defined for the accumulated value to display a warning signal when the accumulated value reaches the limit number.
To achieve the above object, the sixteenth aspect of the present invention is the monitor apparatus for use with a semiconductor test system in the tenth, eleventh and twelfth aspects of the present invention which comprises a filter means for allowing only predetermined signals in the signal information on the tester bus to transfer to the buffer circuit.
To achieve the above object, the seventeenth aspect of the present invention is a monitor apparatus for use with a semiconductor test system which tests a semiconductor device under test by controlling a plurality of relays therein, which is comprised of:
a means for storing a number of ON/OFF operations of the relays under dry condition wherein no electric current flows through contacts of the relays and a number of ON/OFF operations of the relays under wet condition wherein electric current flows through the contacts of the relays; and
a means for analyzing a test history based on the number of ON/OFF operations stored in the storing means.
To achieve the above object, the filter means in the third aspect of the present invention is a filter device comprised of:
a memory means for storing search data therein;
a data comparison means for comparing the search data from the memory means with input data;
thereby producing search results obtained through a binary search process.
To achieve the above object, the filter means in the third aspect of the present invention is a filter device characterized in that a memory means for storing search data therein is a register which stores a 2n value which is closest to and larger than the number of search data.
To achieve the above object, the filter means in the third aspect of the present invention further includes a timing generation means for generating a search timing signal upon receiving a search start signal.
To achieve the above object, the filter means in the third aspect of the present invention includes an address generation means which is comprised of a full adder for performing addition or complement-one addition upon receiving the comparison result from the data comparison means, and a register for storing the result of addition from the full adder.
To achieve the above object, the filter means in the third aspect of the present invention includes:
a buffer for receiving signals on the tester bus of the semiconductor test system;
a gate means for transferring a gate output upon receiving an address bus signal and a data bus signal from the output of the buffer;
wherein a flag indicating a successful search in the binary search process is used as a gate signal for the gate means upon receiving the address signal from the output of the buffer as input data.